A Two-Dimensional Process Model for Chemi-Mechanical Polish Planarization

As device sizes are scaled to sub-micron dimensions, planarization technology becomes increasingly important, both for bipolar and CMOS trench isolation and for multi-level interconnects and wiring. Although chemi-mechanical polishing (CMP) has been used extensively in silicon technology for wafer preparation[l,2], it is only recently that CMP has emerged as a new technique for achieving a high degree of planarization during VLSI processing. One example has been the application of CMP to the fabrication of sub-micron lithography-limited trench isolation[3-5]. The key aspect of CMP is that it is an implicitly non-local process, so that the removal or polish rate at a given point is determined by the topography and the relative heights of the surrounding features. In this way, a degree of planarization can be achieved which is superior to that obtainable by more conventional techniques. However process design can be difficult, since the effects of the polishing will depend on the device layout and the local pattern density. It is thus crucial to develop a model of the CMP process which will allow a full exploitation of the power of this technique, but to date, little has been reported on this subject. Here we describe a relatively simple two dimensional model which, with only 3 adjustable parameters, succeeds in predicting both relative and absolute polish rates for arrays of features under different polishing conditions. The model is extendable to three dimensions, and is also applicable to preferential or selective polishing processes[6,7].